Scientists stack silicon in three dimensions and give Moore’s Law a new lease of life — a breakthrough that could keep computing performance growing for years after traditional miniaturisation hits its limit
A team of researchers at the University of Illinois Urbana-Champaign has demonstrated a method for stacking high-performance silicon circuits directly on top of one another, publishing the results in Nature on May 27, 2026. The technique, known as monolithic three-dimensional integration, achieves near-perfect transistor yields at temperatures well within industrial limits — and may offer the semiconductor industry a viable path forward as traditional miniaturisation runs out of road.
Why Moore’s Law Is Running Out of Room
For decades, chipmakers improved performance by shrinking transistors and packing more onto flat silicon wafers. Those devices are now approaching dimensions where the properties of silicon and the rules of quantum mechanics constrain further reduction.
Professor Cao noted that transistors are no longer shrinking in terms of contacted gate pitch — the key metric by which the industry has long measured progress.
The Heat Barrier That Had Long Blocked 3D Chips
Building circuits upward has long been blocked by heat. Producing high-quality silicon transistors requires temperatures near 1,000 degrees Celsius — far above the 400-degree ceiling that existing metal wiring can tolerate.
The Illinois team used ultrathin single-crystalline silicon nanomembranes — measuring 10 nanometres thick or less — transferred onto completed circuit layers using a roll laminator at no more than 200 degrees Celsius.
What the New Process Actually Builds
The team fabricated three stacked silicon layers, each containing 625 transistors, achieving device yields of 98% to 100% — a result that signals readiness for industrial production.
Transistors in the upper layers delivered performance comparable to standard silicon devices made at far higher temperatures, and performed at least three to four times better than monolithic devices built from alternative materials.
Why Stacking Up Beats Spreading Out
Unlike prior commercial 3D chip approaches — which bond separately manufactured wafers using relatively large through-silicon vias — monolithic integration builds each new layer directly onto the previous one, enabling 10 to 100 times denser vertical connections.
Stacking also shortens internal wiring distances, reducing parasitic capacitance and increasing communication bandwidth — benefits that are particularly significant for artificial intelligence and data-intensive computing workloads.
Industry Partners and the Road to Commercial Foundries
The research was conducted at the University of Illinois Grainger Engineering’s Center for Advanced Semiconductor Chips with Accelerated Performance, whose industry partners include IBM, Intel, and TSMC.
The team is now working to transfer the process to an industrial foundry. The paper was published in Nature on May 27, 2026, with support from the National Science Foundation.
